The AT90SO128 is a low-power, high-performance, 8/16-bit microcontroller with ROM program memory, EEPROM memory, based on RISC architecture microcontroller.

By executing powerful instructions in a single clock cycle, the AT90SO128 achieves throughputs close to 1 MIPS per MHz. Its Harvard architecture includes 32 general purpose working registers directly connected to the ALU, allowing two independent registers to be accessed in one single instruction executed in one clock cycle.

In addition to the 288K Bytes of embedded ROM, the AT90SO128 includes 128K Bytes of high density EEPROM.

The ability to map the EEPROM in the code space allows parts of the program memory to be reprogrammed in-system. This technology combined with the versatile 8/16-bit CPU on a monolithic chip provides a highly flexible and cost-effective solution to many applications.

The USB V2.0 Full Speed controller provides a dynamic pull-up attachment and detachment and a host detection mechanism. It requires a 48 MHz external crystal for the data transfer.

The USB interface provides eight configurable data transfer endpoints, each with its own DPRAM in the memory area. The data transfer type for each endpoint is configured by software. A DMA controller allows a fast communication rate between the RAM of the CPU and the DPRAM.

The High Speed SPI, when configured as a master, provides a clock up to 20MHz thanks to the dedicated internal VFO clock system. A specific DMA controller allows fast transfers between DPRAM banks to CPU RAM. The internal DPRAM memory provides 4 DPRAM buffers of 16 bytes each. The SPI controller features three sources of interrupt (Byte Transmitted, Time-out and Reception Overflow) and a programmable clock and interbytes (guardtime) delays.

The I2C interface interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. Arbitration of the bus is performed internally and puts the I2C in slave mode automatically if the bus arbitration is lost.